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MPC105EVB/d (motorola order number) 7/94 powerpc, powerpc 604, and ps/2 are trademarks of international business machines corp. used by motorola under license from ibm corp. and windows nt is a trademark of microsoft corporation. this document contains information on a new product under development. speci?cations and information herein are subject to change without notice. ? motorola inc. 1994 ? big bend technical summary adv ance inf or mation mpc603/mpc604 ev aluation system big bend t ec hnical summar y this document describes an e v aluation system that demonstrates the capabilities of tw o po werpc? microprocessorsthe mpc603 or mpc604. the system, named big bend, is a po werpc reference platform (prep) compliant design. the motherboard inside the big bend system is an 8-layer pcb design, baby a t -size (9-inch x 13-inch) form f actor , and uses the mpc105 processor to pci bridge de vice for core logic. other major components on the motherboard include the umc pci-isa bridge, national semiconductor s super i/o controllers, and ncr s scsi controller . big bend pro vides an e xample that can be used in designing other systems using po werpc microprocessors. in addition to the big bend ev aluation system, an e v aluation kit containing design information and a manuf acturing kit containing in-depth manufacturing information are available. 1.1 system features the main features of the big bend system are as follows: ? prep compliant mpc603/mpc604 evaluation system ? desktop system in baby at form factor ? supports mpc603 and mpc604 with external bus speeds up to 66 mhz ? processor to pci bridge with motorola mpc105 ? pci to isa bridge with umc um8886 ? onboard national semiconductor pc87323 super i/o chip supports two 16550 serial ports, one parallel port, ?oppy, keyboard, mouse, and ide interface
2 big bend technical summary motorola ? onboard ncr53c825 scsi controller to support the scsi hard drive and cd rom ? high performance pci graphics ? second-level cache selectable between 256 kbyte, 512 kbyte or 1 mbyte ? supports onboard dram up to 128 mbyte; support for 4-mbyte, 8-mbyte, 16-mbyte, and 32- mbyte simms ? three 16-bit isa bus slots and three 32-bit pci bus slots ? standard 101 ps/2?-style keyboard ? supplied with windows nt? operating system and selected applications pre-installed on hard drive 1.2 system bloc k dia gram figure 1 shows the block diagram for the big bend motherboard:
motorola big bend technical summary 3 figure 1. system block diagram 1.3 p erf ormance the key goal for the big bend design is high performance at a reasonable cost. the following timing indicates the number of clock cycles the mpc105 takes for different operations. it is based on the 66-mhz processor b us frequency , 33-mhz pci frequenc y , 64-bit 60x b us and 60-ns dram and 1 mbyte of l2 cache with a 9-ns access time; see table 1. mpc603/mpc604 mpc105 cache memory memory module pci-isa bridge pci slots pci scsi controller ncr53c825 um8886 60x bus pci bus isa bus isa slots real time clock ds1387 super i/o controller pc87323 host to pci bridge isa bus interface module pci bus interface module processor interface module clock module module logic analyzer connector
4 big bend technical summary motorola 1.4 har d ware over vie w the system block diagram shown in figure 1 has seven modules that are now described in turn. ? clock module ? processor interface module ? host to pci bridge ? memory module ? cache memory module ? pci bus interface module ? isa bus interface module 1.4.1 cloc k module figure 2 shows the clock module on the big bend system. table 1. performance analysis processor to memory l2 cache hit number of cycles burst read 3-1-1-1 burst write 3-1-1-1 read followed by pipelined write 3-1-1-1-2-1-1-1 pci to memory l2 cache hit number of cycles burst write 2-1-1-1-1-1-1-1 on-chip cache (mpc603/mpc604) and l2 miss number of cycles burst read 9-1-1-1-1-1-1-1 burst write 2-1-1-1-1-1-1-1 processor to pci burst read 12-2-2-2
motorola big bend technical summary 5 figure 2. clock module there are two clock drivers on the big bend systemthe ics av9154-06 and the motorola mc88pl117. the a v9154-06 uses an e xternal 14.31818 mhz crystal input. external jumpers tied to the fsel(0:2) inputs on the a v9154-06 determine the sysclk frequenc y (25 mhzC66 mhz), which dri v e the mc88pl117. mc88pl117 uses the sysclk input to generate the required frequencies for the processor , the mpc105, the ta g ram, the pci b us, the scsi interf ace, and the pci-isa bridge. the a v9154-06 also generates the clock signal required for the super i/o chip, the osc signal on the isa bus, and also a 128-khz signal for the suspend refresh mode of the mpc105. the mc88pl117 utilizes an internal phase-lock ed loop to create multiple frequencies, and has lo w-skew, large fan-out driving capability . the mc88pl117 has a total of 14 high current outputs with output frequencies referenced to the sysclk frequenc y . t able 2 sho ws the frequencies that are used in the big bend system. 14-mhz crystal av9154-06 14 mhz 24 mhz 128 khz sysclk mc88pl117 fsel(0:2) jumpers sysclk processor mpc105 tag ram pci bus scsi interface pci-isa bridge (from 25 to 66 mhz) (from 25 to 66 mhz)
6 big bend technical summary motorola 1.4.2 pr ocessor interface module figure 3 shows the processor interface module system. figure 3. processor interface module the mpc603 or mpc604 processor generates the internal operating frequenc y using internal phase-lock ed loop circuitry . the mpc603 has the x1, x2, x3, and x4 options and the mpc604 has the x1, x1.5, x2, and x4 options. these options are controlled through the pll (0:3) signals. refer to the mpc603 and mpc604 user s manuals for more information on each of these settings. jumpers are pro vided on the big bend motherboard to con?gure the pll (0:3) pins. the pll(0:3) pins should be con?gured for the desired frequency prior to power-up. a 160-pin logic analyzer connector is located onboard for debugging purposes. 1.4.3 host to pci bridg e module figure 4 shows the block diagram of the mpc105. table 2. supported frequencies mpc603/mpc604 mpc105 pci bus clock external clock frequency internal clock frequency external clock frequency internal clock frequency 40 mhz 80 mhz 20 mhz 40 mhz 20 mhz 25 mhz 75 mhz 1 25 mhz 25 mhz 25 mhz 33 mhz 66 mhz 33 mhz 33 mhz 33 mhz 33 mhz 100 mhz 2 33 mhz 66 mhz 33 mhz 66 mhz 66 mhz 33 mhz 66 mhz 33mhz 66 mhz 100 mhz 33 mhz 66 mhz 33 mhz 1 80-mhz processor operating at 75 mhz 2 powerpc 604 ? microprocessor only 60x bus mpc105 l2 cache logic analyzer connector mpc603/mpc604 memory
motorola big bend technical summary 7 figure 4. mpc105 block diagram the mpc105 is the single-chip prep compliant bridge de vice pro viding access between the mpc603/mpc604 processor and the pci b us. mpc105 also inte grates a secondary cache controller and a high performance memory controller that supports dram or sdram, and r om or flash r om. in the big bend design, up to 128 mbytes of onboard dram and 1 mbyte of flash r om are supported. the mpc105 s processor interf ace module handles the processor transactions and performs snoop operations. this interf ace also pro vides the b us arbitration function between the processors, one le v el of address pipelining, and address and data b us parking. the secondary cache controller supports 256 kbyte to 1 mbyte of direct-mapped cache in write-through or write-back mode; either mode can be programmed through an internal con?guration re gister . f or performance reasons, big bend supports the write-back mode as the default. the mpc105 starts both secondary cache and memory accesses in parallel to reduce secondary cache miss latency . the memory c ycle is aborted if there is a hit on the second-le v el cache. nonpipelined b urst transactions can be completed with a timing of 3-1-1-1 clock c ycles. pipeline burst can be completed with timing of 2-1-1-1 clock c ycles. the cache controller interf aces with e xternal ta g ram and synchronous ram. programmable timing is provided to suit various system requirements. the jtag interf ace on the mpc105 pro vides a boundary-scan capability for board testing. the mpc105 pro vides all the test port signals required by the ieee 1149.1 boundary-scan speci?cation. f or more information about jtag, refer to the ieee 1149.1 document. 1.4.4 memor y interface modules figure 5 shows the memory module on the big bend system. 60x bus interface pll jtag interface memory controller cache controller pci interface
8 big bend technical summary motorola figure 5. memory module on big bend the mpc105 s memory interf ace module is designed to support dram or synchronous dram as main memory . big bend supports 4 banks of dram with a maximum of 128 mbytes when using 16-mbit ram. bidirectional b uf fers are needed on the data b us. the enable and direction control are managed by the mpc105. buf fers are added on all the ma, ras and we signals. the mpc105 supports normal cas before ras refresh. in sleep mode, the mpc105 uses the 128-khz clock as a refresh time base. the best case access timing using 60-ns drams at 66 mhz is 7-3-3-3 clock cycles. the mpc105 s memory interf ace module is also designed to support r om or flash r om on either the 60x b us or the pci b us. big bend supports flash r om for easy code update. a 512-kbyte flash r om is located on the 60x bus. 1.4.5 cac he memor y module figure 6 shows the cache memory module on the big bend system. mpc603/mpc604 address data a d buffers flash rom 36-bit simm md control ma cas ras, we ma mpc105
motorola big bend technical summary 9 figure 6. cache memory module big bend supports cache sizes from 256 kbyte to 1 mbyte. the cache interf ace circuitry inside the mpc105 is designed to run at 66 mhz. idt 71216 16k x 15 t a g rams and motorola mcm72ma64 b urst srams are used as the data synchronous ram. the access time is 10 ns for t a g ram and 9 ns for the data srams. big bend supports both write-back and write-through direct-mapped operation. the f astest nonpipelined burst cycle is 3-1-1-1 while the timing for pipelined bursts is 2-1-1-1. the mpc105 provides four signals for interf acing the synchronous b urst srams. external logic (22v10 p al) is required in the big bend system to decode which bytes of the 64-bit double w ord should be selected for the write by decoding the a29Ca31, tbst , and the tsiz0Ctsiz2 signals. currently , parity on the secondary-le vel cache is not supported. mpc105 res match q idt71216 a0-a31 reset sys_clk a29-a31 tbst tsiz0-tsiz2 adsc d we tale tbst tsiz(0..2) we0-we7 cs0-cs1 a we0-we7 we oe d cs0-cs1 a sysclk baa oe d(0..63) d0-d63 burst srams pal (22v10) tag rams mcm72ma64 hit dir ty_i twe t oe dir ty_o ads d we tale baa doe
10 big bend technical summary motorola 1.4.6 pci interface module figure 7 shows the pci interface module on the big bend system. figure 7. pci interface module there are three pci slots av ailable on the big bend system. one slot is dedicated to the graphics controller card and tw o slots are a v ailable for other add-on cards. the mpc105 supports a 32-bit multiple xed, address/data b us that can run from 20 mhz to 33 mhz (t able 2). the mpc105 pci interface is compliant with the pci local bus speci?cation, re vision 2.0. it also pro vides buf fers between the pci b us, processor, and memory to impro v e system performance. the mpc105 implements tw o 16-byte processor -to-pci write buffers. these buf fers are split to allo w the store g athering function de?ned in the pci speci?cation. store gathering is important for high performance graphic frame buffer operations in which a whole sequence of consecutiv e writes can be generated by the softw are. one 32-bit processor -to-pci read b uf fer is also implemented. data in this b uffer is not forw arded to the processor until the b uf fer is full or the transaction is completed. between system memory and pci, the mpc105 implements tw o 32-byte pci-to-memory write buf fers. these b uf fers hold tw o cache lines so that back-to-back writes from pci may occur , with pci ?lling one buf fer while the data in the other is forw arded to system memory . one 32-byte pci-to-memory read prefetch b uf fer is also implemented. the mpc105 supports speculati v e read operation while it prefetches the ne xt cache line at the completion of the ?rst pci read operation to enhance the pci-to- memory read performance. the scsi interface is pro vided by an ncr53c825 pci scsi controller . it supports both the 8-bit scsi ii interf ace and the 16-bit wide scsi interf ace (both connectors are located on the big bend system). both the cd rom and the hard disk in the big bend system are accessed via the scsi interface. 1.4.7 isa bus interface module figure 8 shows the isa bus interface module. pci slots ncr53c825 scsi controller scsi ii wide scsi mpc105 pci bus
motorola big bend technical summary 11 figure 8. isa bus interface module big bend uses the umc um8886 pci-isa controller as a bridge to the isa b us. the um8886 pro vides the following functions: ? 100% pci and isa compatible ? incorporates two 8237 dma controllers ? high performance pci arbiter ? incorporates two 8259 interrupt controllers ? one 82c54 16-bit counter/timer big bend uses the national pc87323 super i/o controller to pro vide the functionality of tw o(16550 uart- compatible) serial ports, one bidirectional parallel port, an 8042 compatible k e yboard controller , a ps/2- style k e yboard and mouse interf ace, an 82077 compatible ?opp y disk controller interf ace, and an ide interface. the pc87323 is connected to the isa bus. the real time clock function is pro vided by the dallas semiconductor ds1387 controller . it also contains a 4k nonvolatile ram for storing system con?guration data. three isa slots are located on the big bend system. each can support a standard 8-bit or 16-bit isa add- on card. pci-isa controller um 8886 pci bus isa bus super i/o controller pc87323 rtc ds1387 isa slots serial ide floppy parallel keyboard mouse
12 big bend technical summary motorola 1.5 firmware the big bend ?rmw are is pro vided by the motorola risc softw are di vision. the ?rmw are performs the following tasks: ? initializes chipset registers ? tests motherboard hardware ? performs memory sizing ? initializes the interrupt controller ? con?gures the pci interface card ? initializes console to text mode ? initializes boot device ? loads and executes the os loader 1.6 system con?guration the following list provides the standard system con?guration for big bend: ? 80-mhz mpc603 powerpc microprocessor ? 32-mbyte memory on board ? 3.5-inch and 5.25-inch diskette drives ? 500-mbyte scsi hard drive ? cd rom drive with scsi ii interface ? windows accelerated video card w/4-mbyte vram ? ethernet card ? baby-at desktop case ? three 16-bit isa slots ? three pci slots ? ps/2-style keyboard and mouse ? windows nt operating system pre-installed 1.7 documentation big bend is shipped with an e v aluation kit and a manuf acturing kit, which contain the follo wing documentation: the evaluation kit contains the following documents: ? mpc105 technical summary ? mpc603 power management application note ? mpc603 technical summary ? mpc604 technical summary ? big bend technical summary ? bill of materials ? schematicshard copy
motorola big bend technical summary 13 the manufacturing kit contains the following documents: ? mpc105 users manual ? mpc603/mpc604/mpc105 errata sheets ? artworkhard copy ? ball-grid array socket information ? big bend users manual ? board layout and wiring guidelines ? data sheets for other components ? gerber ?le ? prep speci?cation ? schematicssoft copy ? schematics component librarysoft copy
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. there are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters can and do vary in different applications. all operating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?rmative action employer. ibm is a registered tr ademar k of ibm cor p. , p owerpc , and p ow erpc 604 are tr ademar ks of inter national business machines cor p . used b y motorola under license from ibm corp; ps/2 is a trademark of ibm corporation; and windows nt is a trademark of microsoft corporation. motorola literature distribution centers: usa: motorola literature distribution, p.o. box 20912, phoenix, arizona 85036. europe: motorola ltd., european literature centre, 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd., 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd., silicon harbour centre, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. technical information : motorola inc. semiconductor products sector technical responsiveness center; (800) 521-6274. document comments : fax (512) 891-2638, attn: risc applications engineering.

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